(a) Field of the Invention
The present invention relates to a chemical mechanical polishing (CMP) composition and a method for planarizing a semiconductor device using the same. Specifically, the present invention relates to a CMP slurry composition that is used for an interlayer dielectric and in a shallow trench isolation (STI) process during a CMP process conducted for obtaining a semiconductor multi-layer wiring structure, and can largely improve polishing performance, polishing efficiency and selectivity, and simplify the STI CMP process, and a method for planarizing a semiconductor device using the CMP slurry composition.
(b) Description of the Related Art
Tendencies for semiconductors to have high performance and a high integration degree have made the designs of microcircuit devices finer yearly, and thus multi-layer wiring structures are essentially required for designing and manufacturing VLSI and ULSI semiconductor devices. Since the depth of focus a photolithography process becomes shallow and a process margin decreases as the whole wiring width becomes finer and multi-layered, the necessity for planarizing the pattern-forming surface to remove height differences has arisen.
So far, spin-on-glass, resist etch back, etc. have been suggested and used for such planarizing methods. However, planarity sufficient for manufacturing advanced VLSI and ULSI semiconductor devices could not be obtained by said methods. Accordingly, chemical mechanical polishing methods have been suggested, continuously studied and developed, and recently the range of the applications thereof has become very wide. Examples of the applications include polishing of silicon dioxide (SiO2) used for an interlayer dielectric and in an STI process, polishing of a metal wiring layer and interlayer via metal, consisting of tungsten, aluminum (or aluminum alloy), copper, etc., polishing of polysilicon layer used for a deep trench capacitor or a multi-layer gate oxide that were suggested because of the tendency of DRAM to have high capacity and high integration degree, etc. In addition to these commercially applicable CMP processes, a variety of CMP processes will be able to be applied from now on. The examples include a CMP process for low k (interlayer dielectric) material recently high-lighted with a Cu Dual Damascene process. Such low k material includes inorganic HSQ (hydrogen silsequioxane), macromolecule BCB (bisbenzocyclobutene), fluorine-containing organic film and various porous membranes, etc.
Recently, one of the device separation methods, Shallow Trench Isolation (STI) has attracted a great deal of attention as a technology essential for densification of semiconductor devices. This method comprises preparing a shallow trench on a silicon wafer, depositing SiO2 thereon and planarizing it with CMP, and it enables device separation in a smaller area than a conventional local oxidation of silicon (LOCOS) method that causes a bird's beak structure, and it has excellent performances.
However, conventional polishing slurry could not obtain a sufficient polishing selectivity rate of SiO2 and Si3N4, and thus there was no choice but to use a complicated Reverse Moat Process. FIG. 1 schematically shows a process chart of a method for planarizing semiconductor devices using a conventional Reverse Moat Process. This method comprises the steps of a) forming a silicon nitride film on a semiconductor substrate, b) forming a trench on the semiconductor substrate, c) forming an oxide film on top of the trench and the semiconductor substrate, d) reverse moat etching the semiconductor substrate on which the oxide film forms, e) polishing the reverse moat etched semiconductor substrate using a CMP slurry composition, and f) stripping the nitride thin film of the polished semiconductor substrate. Step d) is conducted in order to prevent problems in step f) due to SiO2 residues on Si3N4 layer. However, said method is too complicated, and thus process margin security and productivity decrease.